High speed multiplier/accumulators are well known in the art and are typically used in signal processing systems and in special purpose Fast Fourier Transform (FFT) machines where emphasis is placed on high speed data processing. Although repeated multiply/accumulate operations are the most fundamental in digital signal processing, a problem exists in that they are the most time consuming. Thus, the limitation on the performance of the signal processing system is usually determined by the speed at which these operations can be performed. Because of throughput requirements and real time constraints it is not practical to implement these operations using a general purpose central processing unit (CPU). In the past, special high speed multiplier/accumulators were constructed on printed circuit (PC) boards using small and medium scale integrated circuit technology. However, a problem existed in that the resulting devices were bulky slow and expensive.
Due to advancements in integrated circuit technology, very large scale integrated circuit technology techniques (VLSI) have permitted hundreds of thousands of transistors to be implemented on a single chip. With the use of VLSI technology, the circuit density and performance of traditional multiplier/accumulators has increased whilst the cost thereof has decreased. However, the processing speed of conventional multiplier/accumulators is still unsatisfactory for certain applications. Thus, there still remains the need for a compact high speed multiplier/accumulator.
Accordingly, it is an object of the present invention to obviate or mitigate the above disadvantages by providing a novel multiplication and accumulation device.